The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each new generation has smaller and more complex circuits that the previous generation. However, these advances have increased the complexity of the semiconductor fabrication process(es). For these advances to be realized, similar developments in manufacturing processes are needed. As features are scaled down from one generation to the next, solutions for reducing defects become more critical. One especially critical fabrication process is the formation of the gate dielectric.
Current rinse technologies experience a trade-off between controlling defect types. For example, rinse technologies which control (e.g., reduce) damage to the semiconductor device often experience an increase in other types of defects, such as, for example, remaining photoresist residue on the device.
Thus, what is needed is an improved rinse process for semiconductor device fabrication.